The present invention relates to a pulse generator circuit for generating pulse signals capable of being used as set signals and reset signals to be supplied, for example, to a flip-flop circuit.
In a semiconductor integrated circuit device, a pulse generator circuit for generating a set signal and a reset signal for a RS flip-flop is generally composed as shown in FIG. 1. This pulse generator circuit has capacitors C1 and C2 respectively coupled between the input/output pins 2A and 2B as well as 2C and 2D of the semiconductor integrated circuit device, and a charge/discharge circuit formed in the semiconductor integrated circuit device for charging/discharging these capacitors C1 and C2. This charge/discharge circuit charges these capacitors C1 and C2, and then discharges the capacitors C1 and C2 at a predetermined timing, thereby generating pulses.
However, it is necessary to externally attach capacitors C1 and C2 having relatively large capacitances so as to compose a pulse generator circuit shown in FIG. 1, thereby complicating the fabricating steps of this pulse generator and increasing the cost. As a semiconductor integrated circuit is highly integrated, the number of input/output pins has a tendency to increase, and it is desired to reduce the number of the input/output pins exclusively for the pulse generator. If the capacitors C1 and C2 are formed in the semiconductor integrated circuit, it is not necessary to provide the input/output pins exclusively for the pulse generator. However, since these capacitors C1 and C2 have relatively large capacitances, a considerably large pattern area is needed when the capacitors C1 and C2 are formed in the semiconductor integrated circuit, resulting in the disturbance of the high integration.